1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a device including a MISFET (Metal Insulator Semiconductor Field Effect Transistor) which is suitable for an analog circuit and whose gate electrodes have a finger structure.
2. Discussion of the Background
In recent years, portable telephones rapidly spread and are widely used. RF circuits used in the portable telephones are changing from circuits using bipolar transistors as a conventional mainstream to circuits using MISFETs due to requirements for cost and size reduction.
Generally, in a MISFET for an analog circuit, a gate length Lg is reduced to increase the current gain and power gain. At this time, in a MISFET structure having one gate electrode, a gate resistance Rg becomes high.
To prevent this, finger-shaped gate electrodes 12 as shown in FIG. 9 are interdigitated. In this structure, an element region 11 surrounded by an element isolation region is formed on the surface of a semiconductor substrate. A plurality of contact regions 16 for connecting a wiring layer (not shown) to the gate electrodes 12 through a dielectric interlayer are arranged outside both sides of the element region 11 along its longitudinal direction.
The plurality of gate electrodes 12 are formed on the surface of the element region 11 via a gate oxide film (not shown). Each gate electrode 12 is connected to a corresponding contact region 16 on both sides of the element region 11. Each contact region 16 has one or more than one contact portions 13, as shown in FIG. 9.
In this case, the gate resistance Rg is given by
Rg=xcfx81s*Lf2/(Lg*Wg)xe2x80x83xe2x80x83(1)
where xcfx81s is the sheet resistance, Lf is the length of a finger, Lg is the gate length, and Wg is the gate width=Lf*(number of fingers).
A maximum operation frequency at which an amplified signal is output from the drain, i.e., cutoff frequency fT (frequency when the current gain is unity) is given by
fT=gm/(2xcfx80(Cgb+Cgs))xe2x80x83xe2x80x83(2)
where gm is the transconductance, Cgb is the capacitance between the gate and the element isolation region, and Cgs is the capacitance between the gate and the element region (source, drain, and channel regions).
A maximum oscillation frequency fmax (frequency when the power gain is unity) is given by
fmax=(fT/2)*(Rout/(Rg+Rch))1/2xe2x80x83xe2x80x83(3)
where Rout is the output resistance, and Rch is the ON resistance.
As is apparent for equations (1) to (3), when the gate resistance Rg increases, the maximum oscillation frequency fmax decreases. As a result, the power gain degrades.
However, the conventional semiconductor device has two problems.
First, when the number of fingers is increased by shortening the length Lf of one finger to reduce the gate resistance Rg, the total area of the contact regions 16 increases. This increases the capacitance Cgb between the gate electrodes 12 and the element isolation region. As a result, as is apparent from equations (2) and (3), the cutoff frequency fT and maximum oscillation frequency fmax decrease. Consequently, the current gain and power gain decrease to degrade the frequency characteristic.
When the plurality of gate electrodes 12 are arranged, as shown in FIG. 9, the widths (thicknesses) of all the gate electrodes 12 can hardly be uniformed.
Due to the optical influence in the lithography process, only gate electrodes L and R on the outer sides have smaller widths than those of the remaining gate electrodes 12. Hence, if the pattern becomes small, and the pitch between the gate electrodes 12 decreases, the widths of the outer gate electrodes L and R become too small. This may cause punch-through.
To solve these problems, dummy gates DG are formed on the outer sides of the outer gate electrodes L and R, as shown in FIG. 10. The same optical influence as that for the remaining gate electrodes 12 is obtained, thereby solving that problem.
However, no effect can be obtained by arranging only one dummy gate DG adjacent to each of the gate electrodes L and R. A plurality of dummy gates, e.g., five or more dummy gates are necessary, as shown in FIG. 9. For this reason, the element region increases due to the dummy gates DG, resulting in an increase in chip size.
As described above, in the conventional devices shown in FIGS. 9 and 10, if the number of fingers is increased to reduce the gate resistance, the area of the contact regions increases. This increases the capacitance between the gate and the element isolation region to degrade the RF characteristic. In addition, the gate electrodes in the finger structure cannot be formed to a uniform width without increasing the element area.
A semiconductor device according to an aspect of the present invention comprises at least one MISFET structure, the MISFET structure comprising an element isolation region formed on a surface portion of a semiconductor substrate to have a closed region, an element region formed on the surface region of the semiconductor substrate to surround the element isolation region, a gate insulating film formed to cover at least a surface of the element region, a contact region formed on the element isolation region, and at least four gate electrodes connected to the contact region and formed on the surface of the element region via the gate insulating film to extend to at least outside the element region.